1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to an LCD device and a method for fabricating the same, to obtain a simplified fabricating process by forming a gate electrode and a pixel electrode from the same material.
2. Discussion of the Related Art
Recently, many efforts have been made to research and develop various types of flat display devices, such as a liquid crystal display (LCD), plasma display panel (PDP), electroluminescent display (ELD), and vacuum fluorescent display (VFD). Today, some of the flat display devices are already used in the various applications. Among the types of flat display devices, liquid crystal display (LCD) devices have been widely used because of the advantageous characteristics of thin size, light weight, and low power consumption. In addition, the LCD devices provide a popular substitute to replace a Cathode Ray Tube (CRT). Furthermore, some LCD devices, for example, an LCD TV and mobile type LCD devices such as a display for a notebook computer, are developed to receive and display broadcasting signals.
However, despite the various technical advancements in developing the LCD technology, research in enhancing the picture quality of the LCD device has been, in some respects, lacking the attention as compared to other features and advantages of the LCD device. To use the LCD devices in various fields as a general display, the key to developing the LCD devices depends on whether the LCD devices can realize a high quality picture, such as high resolution and high luminance with a large-sized screen, while still maintaining lightness in weight, thin size, and low power consumption.
In general, the LCD device includes an LCD panel for displaying an image and a driver for supplying a driving signal to the LCD panel. In addition, the LCD panel includes first and second substrates bonded to each other. A liquid crystal layer is interposed in a cell gap between the first and second substrates. The first substrate (referred to as a TFT array substrate) includes a plurality of gate lines arranged in a first direction at fixed intervals, a plurality of data lines arranged in a second direction perpendicular to the first direction at fixed intervals, a plurality of pixel electrodes arranged in a matrix-type configuration within the pixel regions defined by the gate and data lines, and a plurality of thin film transistors formed at appropriate intersection of the gate line and data line, in which each TFT transistor transmits signals from the data lines to the pixel electrodes in accordance with the signals supplied to the gate lines.
The second substrate (referred to as a color filter array substrate) includes a black matrix layer that prevents a light leakage from corresponding portions of the first substrate except at the pixel regions, an R/G/B color filter layer for displaying various colors, and a common electrode for producing an image. Alignment layers are respectively formed on the opposing surfaces of the first and second substrates, wherein the alignment layers are rubbed to align the liquid crystal layer. Then, the first and second substrates are bonded together by a sealant, and liquid crystal is injected between the first and second substrates. In the meantime, the first and second substrates are fabricated by photolithography using several masks, for example, a 5-mask process. Instead of the 5-mask process, a 4-mask process using a diffraction exposure method is gaining popularity for improving the TFT transistor yield.
A method for fabricating an LCD device using a diffraction exposure according to the related art will be described with reference to FIGS. 1A to 1G. As shown in FIG. 1A, a substrate 40 including a plurality of pixel regions is prepared. Then, a metal layer is deposited on an entire surface of the substrate 40, and then selectively patterned by photolithography. Thus, a gate line (not shown) and a gate electrode GE are formed in each of the pixel regions (first mask).
Referring to FIG. 1B, a silicon oxide layer SiOx or silicon nitride layer SiNx is formed on the entire surface of the substrate 40 including the gate electrode GE. Then, a semiconductor material 41 of genuine amorphous silicon, an impurity semiconductor material of amorphous silicon having impurity ions, and a metal layer 43 of chrome or molybdenum are deposited in sequence.
As shown in FIG. 1C, a photoresist PR layer is disposed on an entire surface of the metal layer 43, and then selectively exposed and developed using a diffraction mask M. At this time, the diffraction mask M includes an open part m1 penetrating light, a closed part m2 cutting off the light, and a diffraction part m3 comprised of a slit penetrating some of the light and cutting off some of the light. The diffraction part m3 corresponds to a channel region of the thin film transistor.
When performing the exposure and development process to the photoresist PR by irradiating ultraviolet ray through the diffraction mask M, the photoresist PR corresponding to the open part m1 is removed, the photoresist PR corresponding to the closed part m2 remains as it is, and the photoresist PR corresponding to the diffraction part m3 is removed at a predetermined thickness (second mask). Generally, the photoresist PR corresponding to the diffraction part m3 will result in reducing the original photoresist PR thickness in half.
After that, the exposed metal layer 43, the impurity semiconductor material of amorphous silicon with impurity 42, and the semiconductor material of genuine amorphous silicon 41 are removed by an etching process using the patterned photoresist PR as a mask. As a result, a semiconductor layer 41a, an ohmic contact layer 42a, and a source/drain metal layer 44 are formed on the gate insulating layer GI above the gate electrode GE.
Then, as shown in FIG. 1D, the entire surface of the patterned photoresist PR is ashed by plasma. At this time, the photoresist PR corresponding to the diffraction part m3 is removed because it has less thickness compared to the other parts of the photoresist PR. Accordingly, the source/drain metal layer 44 corresponding to the diffraction part m3 is exposed.
As shown in FIG. 1E, the exposed source/drain metal layer 44, and the ohmic contact layer formed under the source/drain metal layer 44 are simultaneously etched by using the remaining photoresist PR as the mask. Accordingly, a channel region is formed by exposing the portion of first semiconductor layer 41a. At this time, because of a gap formed on the source/drain metal layer 44 within the channel region, it is possible to form a source electrode SE overlapping one edge of the semiconductor layer 41a, and a drain electrode DE overlapping the other edge of the semiconductor layer 41a. 
As shown in FIG. 1F, a passivation layer of organic insulating layer is deposited on the entire surface of the substrate 40 including the source electrode SE and the drain electrode DE, and then selectively patterned by photolithography, thereby forming a drain contact hole C1 which exposes some of the drain electrode DE (third mask).
As shown in FIG. 1G, a transparent conductive layer is deposited on the entire surface of the substrate 40 including the passivation layer 45, wherein the transparent conductive layer is electrically connected with the drain electrode DE through the drain contact hole C1. Then, the transparent conductive layer is patterned by photolithography, whereby a pixel electrode 46 is formed in the pixel region P (fourth mask).
However, the related art method using the 4-mask process has the following disadvantages. In the related art method using the 4-mask process, the production yield is still low. In addition, when using the 4-mask process, it is difficult to obtain an etching uniformity.